Electrically-erasable programmable read-only Memory (EEPROM) possesses random-bit operations and is ideal in some applications. However, EEPROM is not scalable because of the large two-transistor (2T) design and large operation voltages. Thus, EEPROM has evolved into flash structure historically, where one-transistor (1T) array with block erase method enables device scaling.
However, block erase method of 1T flash architecture abandons the random access feature of EEPROM. For NAND Flash, the serial connected to NAND string inevitably makes the read current very small (<500 nA), leading to slow read speed.
Ideally, if flash (charge-storage) device can be designed with random access write/erase, and fast read speed, together with high scalability and 3D stackability, then such a 3D EEPROM device is probably even more competitive than emerging memory devices such as PCRAM and ReRAM.